1. Field of the Invention
The present invention relates to a fabrication process for a semiconductor integrated circuit device and particularly, to a useful technique that is applied in formation of embedded metal interconnection using a chemical mechanical polishing (CMP) method.
2. Description of the Prior Art
In recent years, a chemical mechanical polishing (CMP) method has been introduced as one of new micro-fabrication techniques in company with development toward higher integration and higher performance of LSI. This technique is disclosed in, for example, U.S. Pat. No. 4,944,836.
Increase in Al interconnect resistance is conspicuous as scaling down of Al interconnection advances and especially in a high performance logic LSI, the increase in interconnect resistance has been a great obstacle in the way of further improvement of the performance. In light of such a situation, embedded Cu interconnection by means of the so-called Damascene process has been under development: Interconnect trenches (and through-holes) are formed in an insulating film deposited on a silicon substrate, then a Cu film whose resistivity is lower than an Al film is deposited on the insulating film and in interiors of the trenches (and the through-holes), thereafter unnecessary part of the Cu film outside the trenches is polished off by chemical mechanical polishing. This technique is disclosed, for example, in the publications of Unexamined Japanese Patent Applications Nos. Hei 2-278822 and Hei 10-214834.
The chemical mechanical polishing (CMP) uses a polishing liquid (a slurry) mainly composed of abrasive grains made of particles of alumina, silica or the like and an oxidizing agent, and a metal surface is removed by a mechanical force of the abrasive grains as oxides produced by an oxidizing action of the oxidizing agent on the surface. As for a polishing liquid (a slurry), the following improvements of technique have been disclosed for example:
A technique is described in the publication of Unexamined Japanese Patent Application No. Hei 7-94455: Aqueous solutions are employed as dispersion media for abrasive grains; as solutes, there can be named: hydrochloric acid, ammonium persulfate, chromium oxide, phosphoric acid, ammonium hydroxide, a mixture of copper ammonium chloride and ammonium hydroxide, a mixture of ammonium hydroxide and hydrogen peroxide and furthermore, mixtures of the aqueous solutions can be used. With such an abrasive grain liquid in use, a polishing speed ratio (R) of a metal film including copper to an insulating film (silicon oxide film) is adjusted so as to be larger than 1 and thereby, controllability of an interconnect film thickness is increased. This publication further describes a technique in which an abrasive grain liquid containing silica particles of an average particle diameter of 0.1 xcexcm or less is used in order to prevent a surface of a metal film including Cu which is comparatively soft from being damaged by alumina abrasive grains.
A technique is described in the publication of Unexamined Japanese Patent Application No. Hei 7-233485: A Cu based metal polishing liquid which contains at least one organic acid selected from aminoacetate and amidosulfuric acid, an oxidizing agent (hydrogen peroxide) and water is used and the polishing liquid exerts almost no etching on Cu or Cu alloy when just being immersed in the polishing liquid, whereas the polishing liquid dissolves Cu or Cu alloy when being polished and an etching speed shows tens of times faster in the polishing than when just being immersed.
A technique is described in the publication of Unexamined Japanese Patent Application No. Hei 8-64594: Corrosion of a metal film surface during polishing or after polishing is suppressed and thereby deterioration in quality of interconnection is prevented from occurring. An abrasive grain liquid is employed in which a chemical component forming an anticorrosive coat on a surface of a Cu containing film when polishing the film is mixed, the chemical component being, for example, benzotriazole, and a 2-aminotiazole derivative salt and a copper salt of an inorganic acid.
A technique is described in the publication of Unexamined Japanese Patent Application No. Hei 8-83780: A polishing agent contains a chemical reagent forming a protective film on a metal film surface and an etching agent of a metal film. The polishing agent is used in chemical mechanical polishing of a film of Cu or a Cu containing metal. The chemical reagent may be, for example, benzotriazole or its derivative and the etching agent may contain, for example, aminoacetate and/or amidosulfuric acid; and an oxidizing agent such as hydrogen peroxide, nitric acid or hypochlorous acid.
In a formation process for embedded metal interconnection by chemical mechanical polishing, part of a metal film is left on an insulating film when a unnecessary portion of the metal film on an insulating film outside interconnection trenches formed in the insulating film is removed by the chemical mechanical polishing: the metal film in a recess on a surface of the insulating film caused by a step profile on a surface of an underlying mass cannot be removed. This metal film residue is a cause for a short between embedded interconnects and therefore, the residue is required to be perfectly removed by over-polishing.
If the over-polishing is conducted, however, a phenomenon occurs that embedded interconnects in interconnect trenches are polished so that the center surface portion of each interconnect is excessively removed compared with a peripheral portion thereof and thereby, the center surface portion is selectively withdrawn inwardly compared with the peripheral portion (called dishing) and at the same time, another phenomenon occurs that a surface portion of an insulating film around the opening of each interconnect trench is selectively polished off and also withdrawn inwardly (erosion). When such phenomena occur, interconnect resistance increases because of reduction in sectional area of embedded interconnects. Besides, a problem as in the case described above arises since the above described dishing and erosion are reflected on surface topography of an insulating film deposited on the embedded interconnects with dishing and erosion and recesses occur on the surface of an insulating film thus deposited.
In particular, when embedded interconnects are formed using Cu or Cu alloy, there is a necessity that a conductive barrier layer such as a TiN (titanium nitride) layer that suppresses diffusion of Cu and shows high adhesiveness to an insulating film is interposed between the insulating film and a Cu (alloy) film since Cu has a nature that Cu is easy to diffuse in an insulating film and poor in adhesiveness to an insulating film. Hence, in the formation process of embedded interconnection using Cu (alloy), it is necessary to over-polish a Cu (alloy) film and over-polish a conductive barrier film, so that dishing and erosion are apt to arise in correspondence to levels of the over-polishing and the over-etching.
It is an object of the present invention to provide a technique that can suppress dishing and erosion which is problematic in formation of embedded metal interconnection by means of a chemical mechanical polishing method.
The above described object and other objects, and new features of the present invention will be apparent from the following description and the accompanying drawings.
Simple description will below be made of outlines of typical aspects of the present invention which are disclosed in the present application:
1. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an insulating film on a body, the insulating film having an opening;
(b) forming a conductive barrier layer in the opening and overlying the insulating film;
(c) forming a metal film on the conductive barrier layer inside the opening and overlying the insulating film, to fill the opening;
(d) removing the metal film outside the opening by means of abrasive-grain-free chemical mechanical polishing;
(e) after the step (d), removing any metal film locally remaining on the conductive barrier layer on the insulating film by means of with-abrasive-grain chemical mechanical polishing; and
(f) after the step (e), removing the conductive barrier layer remaining on the insulating film by means of selective chemical mechanical polishing that selectively polishes the conductive barrier layer relatively to the metal film.
2. A method for fabricating a semiconductor integrated circuit device according to 1, wherein the insulating film has a plurality of layers.
3. A method for fabricating a semiconductor integrated circuit device according to 1, wherein the metal film is made of Cu or alloy containing Cu as a main component.
4. A method for fabricating a semiconductor integrated circuit device according to 1, wherein the abrasive-grain-free chemical mechanical polishing is conducted using a polishing liquid having an abrasive grain concentration less than 0.1 wt % of the combined weight of liquid and the abrasive grains.
5. A method for fabricating a semiconductor integrated circuit device according to 1, wherein the opening is a hole.
6. A method for fabricating a semiconductor integrated circuit device according to 1, wherein the opening is a trench.
7. A method for fabricating a semiconductor integrated circuit device according to 1, wherein in the selective chemical mechanical polishing, a polishing selectivity ratio of the conductive barrier layer to the metal film is at least 10:1.
8. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an insulating film on a body, the insulating film having an opening;
(b) forming a conductive barrier layer in the opening and overlying the insulating film;
(c) forming a metal film on the conductive barrier layer inside the opening and overlying the insulating film, to fill the opening;
(d) removing the metal film outside the opening by means of first chemical mechanical polishing in which a selectivity of the metal film to the conductive barrier layer is at least 5:1;
(e) after the step (d), removing any metal film locally remaining on the conductive barrier layer on the insulating film by means of second chemical mechanical polishing in which a selectivity of the metal film to the conductive barrier layer is lower than that in the first chemical mechanical polishing; and
(f) after the step (e), removing the conductive barrier layer remaining on the insulating film by means of third chemical mechanical polishing in which a selectivity of the conductive barrier layer to the metal film is at least 5:1.
9. A method for fabricating a semiconductor integrated circuit device according to 8, wherein the insulating film has a plurality of layers.
10. A method for fabricating a semiconductor integrated circuit device according to 8, wherein the metal film is made of Cu or alloy containing Cu as a main component.
11. A method for fabricating a semiconductor integrated circuit device according to 8, wherein a polishing selectivity ratio of the metal film to the conductive barrier layer in the first chemical mechanical polishing is at least 8:1.
12. A method for fabricating a semiconductor integrated circuit device according to 8, wherein a polishing selectivity ratio of the metal film to the conductive barrier layer in the second chemical mechanical polishing is at most 3:1.
13. A method for fabricating a semiconductor integrated circuit device according to 8, wherein a polishing selectivity ratio of the conductive barrier layer to the metal film in the third chemical mechanical polishing is at least 10:1.
14. A method for fabricating a semiconductor integrated circuit device according to 8, wherein a polishing selectivity ratio of the conductive barrier layer to the metal film in the third chemical mechanical polishing is at least 20:1.
15. A method for fabricating a semiconductor integrated circuit device according to 8, wherein the conductive barrier layer is made of TiN.
16. A method for fabricating a semiconductor integrated circuit device according to 8, wherein the first chemical mechanical polishing and the second chemical mechanical polishing are respectively conducted using different polishing pads.
17. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an insulating film on a body, the insulating film having an opening;
(b) forming a conductive barrier layer in the opening and overlying the insulating film;
(c) forming a metal film on the conductive barrier layer inside the opening and overlying the insulating film, to fill the opening;
(d) removing the metal film outside the opening by means of abrasive-grain-free chemical mechanical polishing;
(e) after the step (d), removing any metal film locally remaining on the conductive barrier layer on the insulating film by means of with-abrasive-grain chemical mechanical polishing; and
(f) after the step (e), removing the conductive barrier layer remaining on the insulating film by means of a selective removal process that selectively removes the conductive barrier layer relatively to the metal film.
18. A method for fabricating a semiconductor integrated circuit device according to 17, wherein the selective removal process of the step (f) is dry etching.
19. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an insulating film on a body, the insulating film having an opening;
(b) forming a conductive barrier layer in the opening and overlying the insulating film;
(c) forming a metal film on the conductive barrier layer inside the opening and overlying the insulating film, to fill the opening;
(d) removing the metal film outside the opening by means of first chemical mechanical polishing using a first polishing liquid in a state belonging to a corrosive region of the metal film;
(e) after the step (d), removing any metal film locally remaining on the conductive barrier layer on the insulating film by means of second chemical mechanical polishing in which a selectivity of the metal film to the conductive barrier layer is lower than that in the first chemical mechanical polishing; and
(f) after the step (e), removing the conductive barrier layer remaining on the insulating film by means of third chemical mechanical polishing in which a selectivity of the conductive barrier layer to the metal film is at least 5:1.
20. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an insulating film on a body, the insulating film having an opening;
(b) forming a conductive barrier layer in the opening and overlying the insulating film;
(c) forming a metal film on the conductive barrier layer inside the opening and overlying the insulating film, to fill the opening;
(d) removing the metal film outside the opening by means of first chemical mechanical polishing in which a selectivity of the metal film to the conductive barrier layer is at least 5:1;
(e) after the step (d), removing any metal film locally remaining on the conductive barrier layer on the insulating film by means of second chemical mechanical polishing in which a selectivity of the metal film to the conductive barrier layer is lower than that in the first chemical mechanical polishing; and
(f) after the step (e), removing the conductive barrier layer remaining on the insulating film by means of third chemical mechanical polishing in which a selectivity of the conductive barrier layer to the metal film is higher than that in the second chemical mechanical polishing.
21. A method for fabricating a semiconductor integrated circuit device according 20, wherein the third chemical mechanical polishing is conducted using a third polishing liquid containing an anticorrosive.
22. A method for fabricating a semiconductor integrated circuit device according to 21, wherein the anticorrosive includes benzotriazole.
23. A method for fabricating a semiconductor integrated circuit device according to 22, wherein a concentration of benzotriazole included in the third polishing liquid is in the range of 0.001 to 1 wt %.
24. A method for fabricating a semiconductor integrated circuit device according to 22, wherein a concentration of benzotriazole included in the third polishing liquid is in the range of 0.01 to 1 wt %.
25. A method for fabricating a semiconductor integrated circuit device according to 20, wherein the insulating film has a plurality of layers.
26. A method for fabricating a semiconductor integrated circuit device according to 20, wherein the first chemical mechanical polishing and the second chemical mechanical polishing are respectively conducted using different polishing pads.
27. A method for fabricating a semiconductor integrated circuit device according to 20, wherein the second chemical mechanical polishing and the third chemical mechanical polishing are respectively conducted using the same polishing pads.
28. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an insulating film on a body, the insulating film having an opening;
(b) forming a conductive barrier layer in the opening and overlying the insulating film;
(c) forming a metal film on the conductive barrier layer inside the opening and overlying the insulating film, to fill the opening;
(d) removing the metal film outside the opening by means of abrasive-grain-free chemical mechanical polishing using a hard polishing pad;
(e) after the step (d), removing any metal film locally remaining on the conductive barrier layer on the insulating film and the conductive barrier layer on the insulating film by means of chemical mechanical polishing;
(f) after the step (e), removing the conductive barrier layer remaining on the insulating film by means of selective chemical mechanical polishing that selectively polishes the conductive barrier layer relatively to the metal film.
29. A method for fabricating a semiconductor integrated circuit device according to 28, wherein the metal film is made of Cu or alloy containing Cu as a main component.
30. A method for fabricating a semiconductor integrated circuit device according to 28, wherein the conductive barrier layer is made of a material harder than the metal film.
31. A method for fabricating a semiconductor integrated circuit device according to 28, wherein polishing in the step (e) is conducted using a polishing pad softer than that used in polishing in the step (d).
32. A method for fabricating a semiconductor integrated circuit device according to 28,
wherein polishing in the step (d) is conducted using a polishing liquid that has a polishing selectivity ratio of the metal film to the conductive barrier layer of at least 5:1; and
polishing in the step (e) is conducted using a polishing liquid that has a polishing selectivity ratio of the conductive barrier layer to the metal film is at least 5:1.
33. A method for fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) forming an insulating film on a body, the insulating film having an opening;
(b) forming a conductive barrier layer in the opening and overlying the insulating film;
(c) forming a metal film on the conductive barrier layer inside the opening and overlying the insulating film, to fill the opening;
(d) removing the metal film outside the opening by means of abrasive-grain-free chemical mechanical polishing;
(e) after the step (d), removing any metal film locally remaining on the conductive barrier layer on the insulating film by means of with-abrasive-grain chemical mechanical polishing;
(f) after the step (e), removing the conductive barrier layer remaining on the insulating film by means of selective chemical mechanical polishing that selectively polishes the conductive barrier layer relatively to the metal film; and
(g) after the step (f), cleaning the body in a state of light shielding.
34. A method for fabricating a semiconductor integrated circuit device according to 33, wherein the metal film is made of Cu or alloy containing Cu as a main component.
35. A method for fabricating a semiconductor integrated circuit device according to 33, wherein cleaning in the step (g) is conducted in a state of light shielding with an illumination of at most 180 lux.